Teruo Utsumi
Staff Engineer at Aril Inc.
Los Gatos, California, United States
Summary
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Senior🎓
Top SchoolTeruo Utsumi is a seasoned hardware architect and engineer with over three decades of end-to-end experience in system and chip design, specializing in FPGA/ASIC development and accelerator architectures. As a Staff Engineer at Aril Inc. in Los Gatos, CA, he leads architecture and implementation efforts for gate arrays, FPGAs, and ASICs, translating complex requirements into efficient hardware solutions. His career spans pivotal roles at SA Photonics, Mugen Computing, Silicon Graphics, SGI, Algorithimica, and Fujitsu, where he consistently optimized algorithm implementations and collaborated with cross-functional teams and external partners. A UC Berkeley alumnus, he earned a BS and has a proven track record delivering hardware-centric solutions across startups and established tech companies. With a rare blend of system-level thinking and hands-on gate-level optimization, he focuses on FPGA-based accelerators and their applications.
10 years of coding experience
17 years of employment as a software developer
BS, BS at University of California, Berkeley
JapaneseGithub contributions (5)
sjaa/scheduler
May 2015 - Jul 2017
Contributions:182 commits, 49 pushes, 1 branch in 2 years 1 month
sjaa/Events-Generator
Apr 2016 - Apr 2016
Contributions:3 pushes, 1 branch in 1 day
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