Jerry Zhao
Member Of Technical Staff at OpenAI
San Francisco, California, United States
Summary
🤩
Rockstar🎓
Top SchoolJerry Zhao is a Member of Technical Staff at OpenAI and a graduate student researcher in UC Berkeley EECS with a decade of experience building and verifying processor and SoC tooling. He is an active open-source contributor to foundational RISC-V and hardware-design projects—Chisel, Rocket Chip, Chipyard, Gemmini, Spike and FireSim—where his contributions span language-level fixes, simulator enhancements, and CI/build infrastructure. Jerry blends backend systems, DevOps, and hardware design expertise, having added custom ISA support (e.g., MOVN), integrated BOOM/Hwacha designs and Dromajo co-simulation, and exposed new PMP configuration options in Spike. His background includes CPU platform and systems internships at Apple and NVIDIA, reinforcing an ability to move research prototypes toward production-ready toolchains. Based in San Francisco, he frequently focuses on hard-to-see work that stabilizes verification and build systems so large hardware experiments can scale.
10 years of coding experience
3 years of employment as a software developer
Electrical Engineering and Computer Science, Engineering, Electrical Engineering and Computer Science, Engineering at University of California, BerkeleyNorth Penn High School
Github Skills (46)
simulation10
caching10
verilog10
assembly10
c-language10
simulate10
systemverilog10
python10
simulator10
computer-architecture10
architecture10
simulations10
risc-v10
configuration-management10
accelerator10
Programming languages (13)
Github contributions (5)
ucb-bar/chipyard
Apr 2019 - Jan 2023
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Role in this project:
Backend Developer
Backend DeveloperContributions:6 releases, 824 reviews, 409 commits in 3 years 9 months
Contributions summary:Jerry's commits primarily involve adding and modifying configuration files and code related to the example project within the Chipyard framework. They implemented configurations for the Hwacha and BOOM architectures, added support for the Dromajo co-simulator, and made modifications to the testing infrastructure for improved verification. The user's contributions enabled the integration of these new designs within the framework, providing a functional starting point for further development within the Chipyard environment. They also updated the code to align with the latest version of the framework.
rtlout-of-orderhardware-designsvlsicomputer-engineering
ucb-bar/riscv-sodor
Oct 2020 - Jan 2023
educational microarchitectures for risc-v isa
Role in this project:Back-end Developer
Back-end DeveloperContributions:18 reviews, 23 commits, 17 PRs in 2 years 3 months
Contributions summary:Jerry contributed to the educational microarchitectures for RISC-V ISA project by adding support for a custom instruction named MOVN. They modified the microcode, which dictates the low-level behavior of the processor, to include this new instruction. Further contributions included adding a trace analyzer script, which is used to debug and analyze the instruction traces generated by the simulator. Moreover, the user made code changes to support processing of the SodorUCode traces.
risc-visamicroarchitecturesriscv32risc
Find and Hire Top DevelopersWe’ve analyzed the programming source code of over 60 million software developers on GitHub and scored them by 50,000 skills. Sign-up on Prog,AI to search for software developers.