Deepeshwar Kumar
Senior FPGA RTL Engineer at Tech Mahindra Cerium Pvt Ltd
Bengaluru, Karnataka, India
Summary
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Senior🎓
Top SchoolDeepeshwar Kumar is a Senior FPGA RTL Engineer with nine years of hands-on experience delivering high-speed digital designs for aerospace, healthcare, and embedded systems. Based in Bengaluru, he has led RTL design and integration on Altera/Xilinx/Intel platforms, including Arria10 deployments, 3.2–6.4 Gbps transceivers, DDR4, and a wide range of high-speed protocols such as AXI, HDMI, USB, Ethernet, and ARINC. His expertise spans the full FPGA lifecycle—from architecture and timing analysis to synthesis, verification, and hardware-software integration—complemented by strong debugging and scripting skills in TCL and Python. Beyond FPGA, he is versed in analog/digital design, signal integrity, power integrity, timing optimization, and avionics-style qualification processes (DO-254). He has contributed to autonomous robotics projects and competitions during his academic and hobbyist work, reflecting a sustained interest in autonomous mobile robotics and embedded systems. He is actively seeking FPGA opportunities to push performance and efficiency in complex systems.
9 years of coding experience
5 years of employment as a software developer
Bachelor of Technology - BTech, ELECTRICAL ENGINEERING, Bachelor of Technology - BTech, ELECTRICAL ENGINEERING at National Institute of Technology Surat
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Github contributions (5)
Deepeshwar/Maze-Solver-Robot
Oct 2017 - May 2019
Contributions:8 pushes in 1 year 8 months
Deepeshwar/dancing-floor
Aug 2016 - Dec 2016
Contributions:2 PRs, 3 pushes, 2 branches in 4 months
floorcapacitivesensing
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