Santosh Malagi
R D DFT Engineer at Siemens EDA (Siemens Digital Industries Software)
Austin, Texas, United States
Summary
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Senior🎓
Top SchoolSantosh Malagi is a focused R&D DFT engineer in Austin with 8+ years delivering EDA software for DFT/ATPG and cell-aware defect extraction across 5nm, 7nm, 16nm, and 28nm nodes. He currently advances Tessent Silicon Lifecycle Solutions at Siemens EDA, shaping next-generation DFT/ATPG capabilities since 2024. Previously at Cadence, he led the Cell-Aware Test (CAT) capability for Modus ATPG, driving methodological improvements in accuracy and performance through modern C++ practices and tooling. A prolific inventor and researcher, he co-authored three issued US patents with a fourth filed in 2024, and contributed to IEEE publications including a best-paper award during his MSc work at imec. Based in Austin, he combines deep C/C++ expertise, Linux systems programming, and a knack for visual technical communication through blog posts to translate complex VLSI/EDA concepts into actionable, cross-domain insights.
8 years of coding experience
7 years of employment as a software developer
Bachelor of Engineering (B.E.), Bachelor of Engineering (B.E.) at Visvesvaraya Technological UniversityKendriya Vidyalaya SangathanMaster of Science (MSc), Master of Science (MSc) at Delft University of Technology
Kannada, Hindi, EnglishGithub contributions (5)
santoshsmalagi/Benchmarks
Dec 2020 - Nov 2021
Contributions:35 commits, 36 pushes, 1 branch in 10 months
santoshsmalagi/CPP
Apr 2020 - Sep 2021
Contributions:661 pushes, 1 branch in 1 year 5 months
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