liuyonggg
Summary
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SeniorYong Liu is a senior architect and AI/EDA hardware-software co-design leader with more than a decade of experience delivering AI platforms, data analytics solutions, and verification tooling across top semiconductor and tech companies. He currently leads the AI and Data Analytics Platform initiative as a Sr. Architect and Sr. Group Director at Cadence Design Systems, based in the San Jose/Cupertino area. Earlier in his career, he built the Kunlun AI chip at Baidu USA for AI inference and training and led formal verification efforts at Synopsys, where Hector emerged as a market-leading data-path tool. As a founding member of NextOp, he helped create the BugScope verification tool that automatically generates RTL assertions, and he has guided RTL/software co-design and verification across multiple organizations, including Atrenta and IDT. He is the TPC Co-Chair for the IEEE International Conference on LLM-Aided Design (2025 onwards), reflecting his leadership in AI-hardware design methodologies. He holds a Master’s in Computer Science from Fudan University and is based in Cupertino, California.
10 years of coding experienceGithub contributions (5)
cocoon333/DSL
May 2016 - Oct 2016
Contributions:17 commits, 14 pushes in 4 months
liuyonggg/learning_python
Oct 2015 - Mar 2016
Contributions:50 pushes, 1 branch in 4 months
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