Paul Zavalney
Distinguished Engineer - IC Archictecture at Silicon Labs
Austin, Texas, United States
Summary
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Rockstar🎓
Top SchoolPaul Zavalney is a Distinguished Engineer in IC Architecture at Silicon Labs, leading RTL and SoC architecture for IoT wireless products from Austin. He advanced from senior design roles into principal and director-level positions, shaping chip and module IP architecture and digital systems strategy across multiple product generations. An active contributor to the RISC‑V ecosystem, his open-source work on CV32E40P and core-v-verif added CSR/debug trigger logic, breakpoint matching and performance-counter support to improve core debug and verification. Trained in devices and materials at UT Austin, he pairs device-level insight with practical RTL and system-level design to bridge silicon implementation and firmware/debug infrastructure.
5 years of coding experience
27 years of employment as a software developer
Electrical Engineer, Devices and Materials, Electrical Engineer, Devices and Materials at The University of Texas at Austin
Github Skills (18)
debugging10
debug10
systemverilog10
uvm10
risc-v10
cpu10
verification10
sys10
systemverilog-hdl10
embedded10
test-automation10
hardware-designs9
verilog9
hardware-design9
fpga8
Programming languages (7)
Github contributions (5)
openhwgroup/cv32e40p
Mar 2020 - Nov 2020
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
Role in this project:
Embedded Systems Engineer / IoT Developer
Embedded Systems Engineer / IoT DeveloperContributions:12 reviews, 39 commits, 28 PRs in 7 months
Contributions summary:Paul focused on modifying and extending the RISC-V processor's CSR (Control and Status Registers) functionality. They implemented debug trigger logic, including adding new CSRs related to triggers and breakpoint matching. The user also addressed illegal instruction exceptions by generating them when accessing unimplemented or blocked CSRs. Their work involved modifying the register file and decoder to handle hardware performance monitor features.
risc-vcpupulpuvmriscv
openhwgroup/core-v-verif
Apr 2020 - Sep 2020
Functional verification project for the CORE-V family of RISC-V cores.
Role in this project:Embedded Systems Engineer / Test Automation Engineer
Embedded Systems Engineer / Test Automation EngineerContributions:1 review, 18 commits, 13 PRs in 4 months
Contributions summary:Paul primarily contributed to the functional verification of a RISC-V core within the `openhwgroup/core-v-verif` repository. Their work included adding and modifying testbench components, specifically integrating debug signals from the memory model and the core testbench. Further contributions involved updating firmware for core tests, enabling performance counters, and adding tests to validate debugger functionality. These changes indicate a focus on testing and verifying the correct operation of the core, especially the debug features.
risc-vsystemverilogriscverificationcores
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