Jérôme Quévremont is a RISC-V and open hardware project leader at Thales Research & Technology in the Greater Paris area, driving collaborative European R&D and standards activity. He holds co-chair and vice‑chair roles in OpenHW Foundation groups and participates in RISC‑V International, bridging industry standardization with hands‑on engineering. With more than 25 years of experience across SoC/ASIC architecture, telecommunications and cybersecurity, he previously led an SoC/ASIC development group and multiple system‑on‑chip projects. He contributes to the open-source RISC‑V ecosystem—notably improving documentation for the CORE‑V CVA6 Linux‑capable core by adding requirements, programmer guidance and virtual memory coverage—making complex microarchitecture topics more accessible to integrators. An MSEE from Télécom Bretagne / IMT Atlantique, he combines university lecturing and conference committee work with practical delivery of trusted computing and microelectronics solutions.
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Role in this project:
Technical Writer
Contributions:93 reviews, 2 commits, 45 PRs in 5 months
Contributions summary:Jérôme primarily contributed to the documentation of the CVA6 processor core. This included creating a requirement specification, a user's guide, and various interface specifications. The user also updated existing documentation, adding sections on virtual memory, the programmer's view, and bit manipulation, improving the overall usability and clarity of the documentation for developers and integrators. The contributions demonstrate a focus on documenting the core's features and functionalities for a broad audience.
Documentation for the OpenHW Group's set of CORE-V RISC-V cores
Contributions:4 PRs, 34 pushes, 1 branch in 2 years 2 months
risc-vrisccores
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