Natesh Raina
Design Verification Engineer
Cupertino, California, United States
Summary
👤
Senior🎓
Top SchoolNatesh Raina is a Design Verification Engineer at Apple in Cupertino, focusing on verification strategies for complex digital designs and computer architecture components. He is a master's student at Georgia Tech in Electrical and Computer Engineering, specializing in Computer Systems and VLSI Design. His prior experience includes a Design Verification Internship at Intel and a Software Engineer in the Audio Domain at Ittiam Systems, complemented by a Graduate Teaching Assistant role at Georgia Tech. At Ittiam, he worked on AAC/HE-AAC codec optimization for x86/x64 and Cortex-A platforms, and helped integrate the USAC decoder into Android's libstagefright with CTS verification for the Android P release. He earned a BE in Electronics and Telecommunication Engineering from Pune Institute of Computer Technology with a 3.77/4.0, bringing a solid mix of embedded and hardware verification expertise to production-grade systems.
10 years of coding experience
2 years of employment as a software developer
Master of Science - MS, Electrical and Computer Engineering, 3.9/4.0, Master of Science - MS, Electrical and Computer Engineering, 3.9/4.0 at Georgia Institute of TechnologyBachelor of Engineering (B.E.), Electronics and Telecommunication Engineering, 3.77/4.0, Bachelor of Engineering (B.E.), Electronics and Telecommunication Engineering, 3.77/4.0 at Pune Institute of Computer TechnologyHigh School Graduate, Science, High School Graduate, Science at K.C. PUBLIC SCHOOL
Hindi, English, Kashmiri
Github Skills (12)
datastructures7
offline-app6
search-engine5
algorithm5
sorting-algorithms4
energy3
explore3
machine-learning2
python2
scheduling1
dataflow1
neural-networks1
Programming languages (3)
Github contributions (5)
rishnat/verilog
Jun 2017 - Aug 2018
Contributions:17 pushes, 1 branch in 1 year 1 month
rishnat/data-structures_algorithms
Mar 2019 - May 2019
Contributions:3 pushes, 1 branch in 2 months
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