Sagar Karandikar
(incoming) Assistant Professor, Electrical Engineering And Computer Sciences at University of California, Berkeley
Berkeley, California, United States
Summary
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Rockstar🎓
Top SchoolSagar Karandikar is a Research Scientist with 13 years of experience and an incoming Assistant Professor in EECS at UC Berkeley. He specializes in RISC-V toolchains and SoC design frameworks, contributing to high-profile open-source projects like Chipyard and riscv-tools. His engineering focus is build and release automation—integrating QEMU, managing submodules, and hardening build scripts to ensure reproducible toolchains and scalable FireSim setups. Sagar uniquely bridges systems research and hands-on release engineering, tackling practical issues such as dependency/version management and build-time limits to make complex research artifacts production-ready. Based in Berkeley, he accelerates adoption of academic hardware research by turning prototypes into reliable, usable infrastructure.
13 years of coding experience
9 years of employment as a software developer
Doctor of Philosophy (Ph.D.) Computer Science, Doctor of Philosophy (Ph.D.) Computer Science at University of California, Berkeley
Github Skills (14)
risc-v10
git10
sh10
script10
bash10
shell10
scripting10
build-automation10
cicd10
qemu10
git-submodules9
automation9
automations9
management9
Programming languages (11)
Github contributions (5)
riscv-software-src/riscv-tools
Jul 2014 - Feb 2016
RISC-V Tools (ISA Simulator and Tests)
Role in this project:
Automation Engineer / Build & Release Engineer
Automation Engineer / Build & Release EngineerContributions:22 commits, 2 PRs, 4 pushes in 1 year 6 months
Contributions summary:Sagar primarily focused on integrating and managing the riscv-qemu component within the riscv-tools repository. Their work involved adding, removing, and building the qemu component using build scripts. They also addressed submodule references and potentially managed build dependencies and version upgrades, demonstrating their skills in build system management and toolchain integration.
risc-visariscvsimulatorrisc
ucb-bar/chipyard
Sep 2019 - Oct 2022
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Role in this project:Automation Engineer / Build & Release Engineer
Automation Engineer / Build & Release EngineerContributions:3 releases, 39 reviews, 118 commits in 3 years 1 month
Contributions summary:Sagar primarily focused on build and release automation within the Chipyard project. Their contributions include modifying build scripts, setting up environment variables, and streamlining the build process for toolchains and dependencies. The user's work also involved fixing issues related to open file limits and improving the setup scripts for the FireSim environment. Additionally, they updated the submodule management and configuration files to ensure build reproducibility and proper submodule initialization.
rtlout-of-orderhardware-designsvlsicomputer-engineering
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