Bill Mcspadden
Formal Verification Engineer
Chanhassen, Minnesota, United States
Summary
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Rockstar🎓
Top SchoolBill Mcspadden is a formal verification engineer in Chanhassen, Minnesota who brings over three decades of VLSI design and verification experience to modeling RISC‑V processors and their ratified extensions. He currently develops the formal RISC‑V processor model at RISC‑V International and has been an active contributor to the ecosystem—serving as vice‑chair of the Architectural Test SIG and working on instruction trace, fast interrupt, cache management, and virtual memory groups. His career includes principal verification roles at Seagate and Starkey, a verification consultancy focused on Verilog/SystemVerilog/OVM/UVM, and a long tenure at Intel on processors and chipsets. That mix of standards work, hands‑on RTL verification, and formal methods gives him a rare perspective on both silicon validation and ISA ecosystem interoperability. He’s skilled at turning nuanced ISA and microarchitectural behaviors into rigorous, auditable formal models that improve correctness across implementations.
4 years of coding experience
34 years of employment as a software developer
Graduate classes in mathematics and programming, Graduate classes in mathematics and programming at Oregon Graduate Institute of Science and TechnologyBachelor’s Degree, Electrical Engineering, Bachelor’s Degree, Electrical Engineering at Texas A&M University
Github Skills (11)
riscv3210
risc-v10
risc10
v-model10
openembedded10
tla8
architecture6
formal-methods5
v-for3
vscode1
vscode-extension1
Programming languages (7)
Github contributions (5)
billmcspadden-riscv/sail-riscv
Aug 2022 - Oct 2024
Sail RISC-V model
Contributions:51 pushes, 12 branches in 2 years 2 months
risc-vriscv-modelsail
billmcspadden-riscv/sail
Feb 2022 - Aug 2023
Sail architecture definition language
Contributions:74 pushes, 1 branch in 1 year 5 months
architecturedefinitionsail
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